1. Field of the Invention
The present invention generally relates to a memory device using a nano tube cell, and more specifically, to a technology of reducing the whole memory size by providing a plurality of nano tube sub cell arrays as a cross point cell in a hierarchical bit line structure including a main bit line and a sub bit line.
2. Description of the Prior Art
Generally, a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) comprises a transistor for performing a switching operation depending on a state of a word line to connect a capacitor to a bit line, and the capacitor connected between a plate line and one terminal of the transistor.
Here, a switching device of a conventional DRAM cell is a NMOS transistor whose switching operation is controlled by a gate control signal. However, when a cell array is embodied by using the NMOS transistor as a switching device, the whole chip size is increased.
Meanwhile, a refresh characteristic of the DRAM cell is determined by the leakage current characteristic of the NMOS transistor. When the channel length of the NMOS transistor is decreased to a nano meter (1/one billion) scale, short channel leakage current increases more by the current characteristic of a sub threshold voltage Sub Vt of the NMOS transistor. As a result, it is difficult to satisfy the refresh characteristic of the DRAM cell. Also, junction leakage current is generated in a storage node terminal which occupies a relatively large area in the DRAM cell.
Specifically, as the capacity of the DRAM increases in embodiment of a DRAM in the giga bite class, the cell size becomes smaller, and also the capacitance of the cell is reduced. In order to stably drive the DRAM cell having small capacitance, capacitance of a bit line is required to be smaller.
Therefore, it is necessary to reduce capacitance of each cell by embodying a bit line structure of the DRAM as a hierarchical bit line structure including a main bit line and a sub bit line, and reduce the whole size by embodying a cross point cell using a capacitor and a PNPN nano tube switch which does not require an additional gate control signal.